Dear TI,
I'm using the SA555 timer to generate a PWM frequency with the circuit shown below. The clock input is generated using another SA555 IC with Ra=Rb=12k and C=20nF.
To vary the PWM in the circuit below CONT (pin 5) is fed using a 0-5V dc signal driven using an-amp. Not matter what the dc level at CONT, the PWM remains fixed frequency. Is the source impedance from the op-amp too low, and can CONT only work when AC coupled?
Thanks, Rob
Hi Rob,
One issue I see is that the duty cycle of your first timer is too low. The output low time of the first timer needs to be less than minimum high time of the PWM output.
I recreated your circuit in TINA-TI and put no voltage on the cont pin (so default is 2/3*Vdd). In this configuration, the second timer has a period of 1.1*3k*20u= 66us. As you can see in the simulation, the second timer attempts to go low after 66us, but the low pulse of the first timer's output is retriggering it. That's why the PWM duty cycle appears to be fixed and mirrors the input clock.
To fix this, you can keep the same frequency of your original timer, but increase RA and lower RB to lower the duty cycle. I found that an RA of 34k, and RB of 1k works for a cont value down to about 1V.
This FAQ post on e2e goes into a lot more detail on this PWM circuit, as well as alternate designs. Figure 2 in that FAQ gives a graph for the output duty cycle vs control voltage. The RC constant you are using in your PWM circuit is 7.56RC=1/F, with F being the input clock frequency. The datasheet example recommends using 4RC= 1/F. The text above figure 2 of the FAQ talks about the differences in linearity of the output duty cycle vs control voltage when using different ratios.
Let us know if you have any other questions.
Best,
Katlynne Jones
